RISC-V Technical Symposium Moscow

co-hosted by SiFive and Syntacore
May 20, 2019. Moscow, Holiday Inn Lesnaya
The RISC-V ISA has spawned a worldwide revolution in the semiconductor industry.

SiFive, the company founded by the inventors of the RISC-V architecture, and Syntacore, a founding member of the RISC-V Foundation and leader in RISC-V processor IP cores, are jointly hosting a RISC-V technical symposium in Moscow on Monday, May 20, 2019 at the Holiday Inn Moscow Lesnaya.

SiFive is fueling the global RISC-V momentum with myriad hardware and software solutions that are democratizing access to custom silicon featuring robust design platforms and custom accelerators. As a result, we are witnessing new and innovative RISC-V based solutions for IoT, AI, networking and storage applications.
Syntacore, a leading provider of RISC-V compatible CPU IP, with a design center in Saint-Petersburg, is instrumental in fostering RISC-V based advancements in technology with one of the widest offerings of customizable cores and tools.

This event will feature presentations by industry veterans, ecosystem partners and researchers from academia. Attendees will learn about custom cores and design platforms, and the SaaS-based approach that is enabling fast and easy access to them. We will also showcase currently-available RISC-V core development boards, high bandwidth memory IP subsystem validation boards and customizable RISC-V SoC platforms, all of which reduce risk, development time and cost while enabling differentiation within silicon.

This symposium is intended for engineers and electronics professionals, electronics-focused academicians, and electronics and electrical associations.
Attendance is free for qualified attendees (preliminary registration required).
Krste Asanovic
Chairman of the Board
RISC-V Foundation,
Chief Architect, SiFive
Alexander Redkin
Executive director
Jaspi Sandhu
Vice President of Sales
Alexander Kamkin
Lead researcher
Pavel Khabarov
Lead Engineer
Jahoor Vohra
Senior FAE
Ekaterina Berezina
Senior Engineer
Felipe Torrezan
Field Application Engineer
IAR Systems
Rupert Baines
Registration is closed
About RISC-V
RISC-V is a free, open, universal and extensible instruction set architecture (ISA), targeted at the wide range of the applications. RISC-V Foundation, a non-profit industry corporation drives development and promotion of the ISA with a primary goal to establish RISC-V as a standard universal processor architecture for all applications.
For more information, visit www.riscv.org.

About SiFive
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital.
For more information, visit www.sifive.com.
About Syntacore
Syntacore is a RISC-V processor IP specialist. Leading provider of the RISC-V compatible processor IP, company creates state-of-the-art, highly-efficient designs that help customers to design comprehensive solutions for the IoT, data storage and processing, embedded systems, cognitive, machine learning and artificial intelligence applications. Syntacore offers turnkey workload-specific customization services for the SCRx cores family that can yield substantial (10x and more) improvements in the performance and/or power-efficiency for the specific workloads.
For more information, visit www.syntacore.com
About UltraSoC
UltraSoC has semiconductor IP for debug (run control, trace, etc) for complex SoCs: making it easy to develop, optimize, fix bugs, reduce power consumption and reduce cost. This can be used pre‐silicon, to accelerate emulation and prototyping, or post‐silicon to support bring up, HW/SW integration or even in‐field/in‐use. UltraSoC has full support for RISC‐V (and other CPUs e.g. heterogeneous multi‐core), but debug addresses not just the CPU but across whole SoC.
For more information, visit www.ultrasoc.com.

About IAR Systems
IAR Systems supplies future-proof software tools and services for embedded development, enabling companies worldwide to create the products of today and the innovations of tomorrow. Since 1983, IAR Systems' solutions have ensured quality, reliability and efficiency in the development of millions of embedded applications. IAR Systems is headquartered in Uppsala, Sweden and has sales and support offices all over the world. IAR Systems Group AB is listed on NASDAQ.
For more information, visit www.iar.com.
15 Lesnaya Street Moscow 125047 Russia, 2 floor, Grand Ball Room

Organized by:
SiFive I Syntacore


Anton Kruzhkov
Phone: +7 (911) 280 35 62
E-mail: events@syntacore.com

Terms and Conditions and Privacy Policy