The RISC-V ISA has spawned a worldwide revolution in the semiconductor industry.
SiFive, the company founded by the inventors of the RISC-V architecture, and Syntacore, a founding member of the RISC-V Foundation and leader in RISC-V processor IP cores, are jointly hosting a RISC-V technical symposium in Moscow on Monday, May 20, 2019 at the Moscow Holiday Inn Lesnaya.
SiFive is fueling the global RISC-V momentum with myriad hardware and software solutions that are democratizing access to custom silicon featuring robust design platforms and custom accelerators. As a result, we are witnessing new and innovative RISC-V based solutions for IoT, AI, networking and storage applications.
Syntacore, a leading provider of RISC-V compatible CPU IP, with a design center in Saint-Petersburg, is instrumental in fostering RISC-V based advancements in technology with one of the widest offerings of customizable cores and tools.
This event will feature presentations by industry veterans, ecosystem partners and researchers from academia. Attendees will learn about custom cores and design platforms, and the SaaS-based approach that is enabling fast and easy access to them. We will also showcase currently-available RISC-V core development boards, high bandwidth memory IP subsystem validation boards and customizable RISC-V SoC platforms, all of which reduce risk, development time and cost while enabling differentiation within silicon.
This symposium is intended for engineers and electronics professionals, electronics-focused academicians, and electronics and electrical associations. Attendance is free for qualified attendees (preliminary registration required).
Chairman of the Board
Chief Architect, SiFive
Vice President of Sales
Field Application Engineer
|09:00 – 10:00||Registration|
|10:00 – 10:10||Welcome and Introduction, by Jaspi Sandhu, VP of Sales, SiFive|
|10:10 – 10:50||RISC-V History and State of the Union, by Krste Asanovic, Chairman of RISC-V Foundation|
|10:50 – 11:10||Professional development tools for RISC-V, Felipe Torrezan, FAE , IAR Systems|
|11:10 – 11:40||Keynote: Leading Semiconductor Design Revolution, by Krste Asanovic, Co-Founder and Chief Architect, SiFive|
|11:40 – 12:00||Break|
|12:00 – 12:20||SCRx family of the RISC-V compatible CPU IP, Pavel Khabarov, Lead Engineer, Syntacore|
|12:20 – 12:40||SoC Level Analytics, Trace & Debug for RISC-V Designs, Rupert Baines, CEO, UltraSoC|
|12:40 – 13:00||MicroTESK for RISC-V: test coverage generation and binary code analysis, by Alexander Kamkin, Lead Researcher, ISP RAS|
|13:00 – 14:00||Lunch and Demos|
|14:00 – 14:20||RISC-V Core IP for Target Vertical Markets, by Jahoor Vohra, Sr. FAE, SiFive|
|14:20 – 14:40||RISC-V software ecosystem overview, by Syntacore|
|14:40 – 15:00||Freedom Revolution: Customizable RISC-V AI SoC Platform, by Krste Asanovic, Co-Founder and Chief Architect, SiFive|
|15:00 – 15:30||Keynote: State o the union RISC-V in Russia, by Alexander Redkin, CEO, Syntacore|
|15:30 – 15:50||Break|
|15:50 – 16:15||Tutorial: SiFive Core Designer, by Jahoor Vohra, Sr. FAE, SiFive|
|16:15 – 16:40||Tutorial: Using SCR1 – open industry-grade MCU class core by Syntacore, Ekaterina Berezina, Senior HW Engineer, Syntacore|
|16:40 – 16:50||Video: Design Your Own CPU|
|16:50 – 17:00||Closing Remarks, by Alexander Redkin, Syntacore|
|17:00 – 18:00||Networking/Demos|
RISC-V is a free, open, universal and extensible instruction set architecture (ISA), targeted at the wide range of the applications. RISC-V Foundation, a non-profit industry corporation drives development and promotion of the ISA with a primary goal to establish RISC-V as a standard universal processor architecture for all applications.
For more information, visit www.riscv.org
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital.
For more information, visit www.sifive.com
Syntacore is a RISC-V processor IP specialist. Leading provider of the RISC-V compatible processor IP, company creates state-of-the-art, highly-efficient designs that help customers to design comprehensive solutions for the IoT, data storage and processing, embedded systems, cognitive, machine learning and artificial intelligence applications. Syntacore offers turnkey workload-specific customization services for the SCRx cores family that can yield substantial (10x and more) improvements in the performance and/or power-efficiency for the specific workloads.
For more information, visit www.syntacore.com
UltraSoC has semiconductor IP for debug (run control, trace, etc) for complex SoCs: making it easy to develop, optimize, fix bugs, reduce power consumption and reduce cost. This can be used pre‐silicon, to accelerate emulation and prototyping, or post‐silicon to support bring up, HW/SW integration or even in‐field/in‐use. UltraSoC has full support for RISC‐V (and other CPUs e.g. heterogeneous multi‐core), but debug addresses not just the CPU but across whole SoC.
For more information, visit www.ultrasoc.com
About IAR Systems
IAR Systems supplies future-proof software tools and services for embedded development, enabling companies worldwide to create the products of today and the innovations of tomorrow. Since 1983, IAR Systems' solutions have ensured quality, reliability and efficiency in the development of millions of embedded applications. IAR Systems is headquartered in Uppsala, Sweden and has sales and support offices all over the world. IAR Systems Group AB is listed on NASDAQ.
For more information, visit www.iar.com